1. Field of the Invention
This invention relates in general to semiconductor devices and methods for fabricating same. More specifically, the invention comprises novel power field effect semiconductor device fabrication methods and structures that include a tungsten silicide/polysilicon/oxide gate stack with low sheet resistance and/or selective low pressure chemical vapor deposited (LPCVD) tungsten layers on the semiconductor wafer to lower ohmic contact resistance.
2. Description of the Prior Art
Gate electrodes in vertical power field effect devices are commonly formed by wet etching or dry etching heavily doped polysilicon/oxide stacks prior to channel and source implantation and diffusion. The lowest attainable gate sheet resistance using this method is typically 20-25 ohms/square, which is due principally to the solid solubility limitation of the dopant (e.g. phosphorous) within the polysilicon layer. For certain applications, such as the high frequency, low voltage power field effect transistors (FETs) discussed below, a gate sheet resistance of 20-25 ohms/square is high and functions to disadvantageously restrict the gate turn-on and turn-off times and results in increased gate switching losses. In addition, non-uniform turn-on and turn-off resistance/capacitance (RC) mechanisms often result which significantly hinder the frequency response of such devices and cause local hot spots.
Over the last several years, switched mode power converter requirements have become more and more sophisticated in order to keep up with the advances being made in high speed very large scale integrated circuits (VLSI) and high density interconnect methods of system packaging. There is presently envisioned a need by some in the industry for low voltage devices (e.g., V.sub.BD =50-100 volts, or less) capable of use for high frequency (1-5 MHz) power switching applications. Such devices will allow local distribution of power to an integrated circuit. In order to accomplish this goal, however, it is necessary to lower gate sheet resistance (i.e., &lt;20-25 ohms/square) to reduce gate distributed RC propagation delay, improve gate switching efficiency, enhance device reliability, and reduce die size for a given current rating by eliminating long gate runners.
Another barrier to obtaining practical high frequency, low voltage power field effect devices is the significant contribution to on-resistance of the device from the source, gate and drain ohmic contacts. To reduce the on-stage power dissipation and to improve the current handling capability of the device, a low specific on-resistance is desired.
It is known in the semiconductor field effect transistor art to convert the surface of a gate electrode to a metal silicide in order to reduce the resistance of the gate structure to lateral current flow. It is also known in the VLSI art in which external metallization does not contact the source region along its length to silicide the surface of the source region to minimize the source region resistance to current flow along its length. Each of these uses of metal silicide is directed to the specific purpose of increasing the conductivity of a particular silicon region in order that the region itself may have a low resistance to the flow of current along the length thereof. Further, prior uses of metal silicide have required additional processing steps and/or placed processing limitations on device fabrication. For example, additional masking and etching are typically necessary, and once deposited, high temperature drive must be avoided.
Reduction of gate sheet resistance and contact resistance have been long term objectives in which each incremental advance improves device performance and yields a competitive edge. Consequently, as new techniques for reducing gate sheet resistance and/or contact resistance have been developed, they have been widely adopted. Therefore, novel field effect power device fabrication methods and structures which provide significant improvement over heretofore obtainable gate sheet resistance and which provide lowered gate, source and drain ohmic contact resistances are clearly desirable and commercially significant.